Materials Science & Nanobiotechnology

Krishna Saraswat, a Ph.D. from Stanford University, USA, is Rickey/Nielsen Chair Professor of Electrical Engineering at Stanford University. His research interests are in new and innovative materials, structures, and process technology of semiconductor devices and metal and optical interconnects for nanoelectronics, and high efficiency and low cost solar cells. He has supervised more than 90 doctoral students, 35 post doctoral scholars and has authored or co-authored over 800 technical papers. He is a Life Fellow of the IEEE. He received the Thomas Callinan Award from The Electrochemical Society in 2000, the  IEEE Andrew Grove award in 2004, Inventor Recognition Award from MARCO/FCRP in 2007, the Technovisionary Award from the India Semiconductor Association in 2007 and the Semiconductor Industry Association Researcher of the Year Award in 2012. He is listed by ISI as one of the 250 Highly Cited Authors in his field.

 

Modern electronics has advanced at a tremendous pace primarily due to enhanced performance of CMOS transistors due to dimension scaling, introduction of new materials and novel device structures. While scaling transistors increases their performance, opposite is true for scaling the copper/low-k interconnects that link these transistors. Looking into the future the relentless scaling paradigm is threatened by the limits of interconnects, including excessive power dissipation, insufficient communication bandwidth, and signal latency for both off-chip and on-chip applications. Many of these obstacles stem from the physical limitation of copper electrical wires, in particular, the increase in copper resistivity, as wire dimensions and grain size become comparable to the bulk mean free path of electrons in copper. Thus, it is imperative to examine alternate interconnect schemes and explore possible advantages of novel potential candidates: carbon nanotubes (CNT), graphene and optical interconnect. Simulations show that CNTs and graphene are advantageous for local interconnects due to their lower resistance, while optical interconnects are better suited for global, semi-global and off-chip interconnects. Ge and GeSn are emerging as viable candidate for Si compatible integration of optical components, laser, detectors and modulators. Three-dimensional (3-D) integration would be a possible way to integrate these on a Si based system on a chip (SoC). The 3-D technology offers the capability to build SoC by placing heterogeneous circuits in different layers, e.g., memory, logic, analog, sensors, wireless and optical I/O, etc. 3-D integration can reduce the chip area and thus improve chip performance by reducing interconnect length, thereby reducing the resistance and capacitance and thus enhance system performance. A review of these emerging interconnect technologies for nanoelectronics will be discussed.